Transistor of volatile memory device with gate dielectric structure capable of trapping charges and method for fabricating the same

ABSTRACT

The present invention relates to a transistor of a volatile memory device with gate dielectric structure capable of trapping charges and a method for fabricating the same. The transistor in a cell region of a volatile memory device includes a substrate of a first conductive type; a gate dielectric structure capable of trapping charges and formed on the substrate; a gate formed on the gate dielectric structure; a gate insulation layer formed on the gate; a source/drain of a second conductive type formed in a predetermined region of the substrate disposed beneath each lateral side of the gate; and a channel ion implantation region of the first conductive type formed in a predetermined region of the substrate disposed beneath the gate.

FIELD OF THE INVENTION

The present invention relates to a volatile memory technology; and, moreparticularly, to a transistor of a volatile memory with a gatedielectric structure of oxide-nitride-oxide and a method for fabricatingthe same.

DESCRIPTION OF RELATED ARTS

As known, each cell in a volatile dynamic random access memory (DRAM)device includes one transistor and one capacitor.

FIG. 1 is a cross-sectional view of a conventional transistor in a cellregion of a DRAM device. Two wells 103 and 104 are sequentially formedin a silicon substrate 101. Since an N-channel transistor is typicallyadopted for the DRAM device, the aforementioned two wells are a deepN-type well 103 formed in the silicon substrate 101 of P-type and a deepP-type well 104 defined within the deep N-type well 103.

Also, a device isolation layer 102 is formed in the silicon substrate101 by performing a shallow trench isolation (STI) process. After theformation of the device isolation layer 102, a field region in which thedevice isolation layer 102 is formed and an active region are defined. Aplurality of gate structures 107 including a gate oxide layer 106 areformed on an active region. Herein, the gate oxide layer 106 is made ofsilicon dioxide (SiO₂). A channel ion implantation region 105 forcontrolling a threshold voltage is formed in each of channel regionsdefined within portions of the P-type well 104 disposed beneath the gatestructures 107. Also, there is a source/drain 108 in each predeterminedregion of the silicon substrate 101 allocated between the gatestructures 107.

The transistor having the above described structure has a thresholdvoltage (V_(TH)) defined as follows. $\begin{matrix}{V_{TH} = {{\Phi_{MS} - \frac{Q_{EFF}}{C_{OX}} + {2 \cdot {\Phi_{F}}} - \frac{Q_{B}}{C_{OX}}}\quad = {\Phi_{MS} - \frac{Q_{EFF}}{C_{OX}} + {2 \cdot {\Phi_{F}}} + \frac{2 \cdot \sqrt{ɛ_{s} \cdot q \cdot N_{\Lambda} \cdot {\Phi_{F}}}}{C_{OX}}}}} & {{Eq}.\quad 1}\end{matrix}$

Herein, ‘Φ_(MS)’, ‘Q_(EFF)’, ‘C_(OX)’, ‘Φ_(F)’, ‘Q_(B)’, ‘ε_(s)’, ‘q’,and ‘N_(A)’ express a linear function between the gate structure 107 andthe channel ion implantation region 105, a charge amount of a totaleffective oxide layer per unit area when a gate voltage (V_(G)) equalsto the threshold voltage (V_(TH)), a capacitance of the gate oxide layerper unit area, a Fermi potential of a semiconductor region, a chargeamount per unit area of a depletion layer in the semiconductor region, apermittivity of the semiconductor region, a charge amount of electrons,and a doping concentration of an impurity implanted into thesemiconductor region, respectively.

The charge amount of the total effective oxide layer per unit area‘Q_(EFF)’ is expressed as follows. $\begin{matrix}{Q_{EFF} = {Q_{SS} + Q_{{it}{({{\Phi\quad S} = {{2 \cdot \Phi}\quad F}})}} + {\int_{0}^{T_{OX}}{\frac{x \cdot {\rho(x)}}{T_{OX}} \cdot {\mathbb{d}x}}}}} & {{Eq}.\quad 2}\end{matrix}$

Herein, ‘Q_(ss)’, ‘Q_(it)’, ‘Φ_(s)’, ‘ρ(x)’, and ‘T_(OX)’ express asurface state fixed charge amount in an interface between thesemiconductor region and the gate oxide layer 106, an interface statecharge amount in an interface between the semiconductor region and thegate oxide layer 106, a surface potential of the semiconductor region,an average charge density of the gate oxide layer 106 measured from aninterface having a distance ‘x ’ between the semiconductor region andthe gate oxide layer 106 to a predetermined distance ‘x+dx’, and athickness of the gate oxide layer 106, respectively.

Therefore, on the basis of the equations 1 and 2, the threshold voltage(V_(TH)) of the transistor in a cell region can be defined as follows.$\left. {V_{TH} = {\Phi_{MS} - {\frac{1}{C_{OX}} \cdot \left\lbrack {Q_{ss} + Q_{{it}({{\Phi\quad s} = {{2 \cdot \Phi}\quad F}}}} \right)} + {\int_{0}^{T_{OX}}{\frac{x \cdot {\rho(x)}}{T_{OX}} \cdot {\mathbb{d}x}}}}} \right\rbrack + \quad{2 \cdot {\Phi_{F}}} + \frac{2 \cdot \sqrt{ɛ_{s} \cdot q \cdot N_{\Lambda} \cdot {\Phi_{F}}}}{C_{OX}}$

Meanwhile, advancement in DRAM technology has led to a gradual decreasein a minimum design rule, which in turn, causes a channel length and awidth of the transistor of the DRAM device to be decreased. Thus, thethreshold voltage of the transistor decreases because of a short channeleffect and an inverse narrow width effect. As a result of this decreasedthreshold voltage, a punch-through phenomenon more frequently occursbetween a source and a drain.

However, for a normal operation of the DRAM device, it is necessary tomaintain the threshold voltage of the transistor of the DRAM device, anda voltage inducing the punch-through phenomenon should be higher than anoperation voltage.

Therefore, doping concentrations of a channel region and a well regionof the transistor need to be increased in order to obtain a decrease inthe threshold voltage and to prevent the punch-through phenomenon. Thatis, as shown in the equation 3, a value of ‘V_(TH)’ is increased byincreasing a value of ‘N_(A)’, a width of a depletion layer between thesource and the drain is decreased to increase the voltage inducing thepunch-through phenomenon.

Nevertheless, the increase in the doping concentration of the channelregion and the well region causes potentials of the source and the drainto be increased, further resulting in adverse effects of increasingjunction leakage and deteriorating a refresh characteristic of the DRAMdevice. These described adverse effects are shown in FIGS. 2A and 2B.Particularly, FIG. 2A is a graph showing that the junction leakageincreases as a doping concentration of boron into the P-type wellincreases. FIG. 2B is a graph showing that a data retention timedecreases as the doping concentration of the P-type well increases.

As described above, in the transistor of the conventional DRAM device,the threshold voltage characteristic, the punch-through characteristicand the refresh characteristic have an offset relationship with eachother. Characteristics of the transistor of the DRAM device are retainedthrough compromising those characteristics.

However, as the design rule of the DRAM device has been decreased to thesize less than 100 nm, it may become much difficult to satisfy thethreshold voltage characteristic, the punch-through characteristic andthe refresh characteristic simultaneously only by increasing the dopingconcentrations of the channel region and the well region.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide atransistor of a volatile memory device capable of obtaining an intendedlevel of a threshold voltage along with a lowered doping concentrationof a channel ion implantation region and a method for fabricating thesame.

In accordance with an aspect of the present invention, there is provideda transistor in a cell region of a volatile memory device, including: asubstrate of a first conductive type; a gate dielectric structurecapable of trapping charges and formed on the substrate; a gate formedon the gate dielectric structure; a gate insulation layer formed on thegate; a source/drain of a second conductive type formed in apredetermined region of the substrate disposed beneath each lateral sideof the gate; and a channel ion implantation region of the firstconductive type formed in a predetermined region of the substratedisposed beneath the gate.

In accordance with another aspect of the present invention, there isprovided a volatile memory device, including: a first transistor for usein a memory cell provided with a gate dielectric structure including: abottom gate dielectric layer; a middle gate dielectric layer fortrapping charges; and a top gate dielectric layer; and a secondtransistor for use in a logic circuit provided with a gate dielectricstructure of a single oxide layer.

In accordance with still another aspect of the present invention, thereis provided a volatile memory device, including: a first N-channel metaloxide semiconductor (NMOS) transistor for use in a memory cell providedwith a gate dielectric structure including: a bottom gate dielectriclayer; a middle gate dielectric layer; and a top gate dielectric layer;a second NMOS transistor for use in a logic circuit provided with a gatedielectric structure of a single oxide layer; and a P-channel metaloxide semiconductor (PMOS) transistor for use in a logic circuitprovided with a gate dielectric structure including; a bottom gatedielectric layer; a middle gate dielectric layer; and a top gatedielectric layer.

In accordance with still another aspect of the present invention, thereis provided a volatile memory device, including: a transistor for use ina memory cell, the transistor including: a substrate of a firstconductive; a gate dielectric structure capable of trapping charges andformed on the substrate; a gate formed on the gate dielectric structure;a gate insulation layer formed on the gate; a source/drain of a secondconductive type formed in a predetermined portion of the substratedisposed beneath each lateral side of the gate; and a channel ionimplantation region of the first conductive type formed in apredetermined region of the substrate disposed beneath the gate; and avoltage generating unit for controlling a threshold voltage of thetransistor for use in the memory cell by implanting charges to the gatedielectric structure through supplying a predetermined voltage to eachof the substrate, the gate and the source/drain.

In accordance with still another aspect of the present invention, thereis provided a method for forming a gate dielectric structure of avolatile memory device, wherein the volatile memory device is definedwith a cell region where a transistor for use in a memory cell is formedand a peripheral region where a transistor for use in a logic circuit isformed, including the steps of: sequentially forming a first oxidelayer, a dielectric layer for trapping charges and a second oxide layeron a substrate; selectively etching the second oxide layer and thedielectric layer disposed in the peripheral region; etching the firstoxide layer exposed in the peripheral region as simultaneously asetching the second oxide layer in the cell region; and forming a thirdoxide layer in the cell region and in the peripheral region.

In accordance with still another aspect of the present invention, thereis provided a method for forming a gate dielectric structure in avolatile memory device, wherein the volatile memory device is definedwith a cell region where a first NMOS transistor for use in a memorycell is formed and a peripheral region where a second NMOS transistorfor use in a logic circuit and a PMOS transistor for use in a logiccircuit are formed, the method including the steps of: sequentiallyforming a first oxide layer, a dielectric layer for trapping charges anda second oxide layer on a substrate; selectively etching the secondoxide layer and the dielectric layer in a first predetermined region ofthe peripheral region where the second NMOS transistor is formed;removing the first oxide layer exposed in the first predetermined regionas simultaneously as etching the second oxide layer disposed in the cellregion and in a second predetermined region of the peripheral regionwhere the PMOS transistor is formed; and forming a third oxide layer inthe cell region and in the peripheral region.

In accordance with further aspect of the present invention, there isprovided a method for forming a gate dielectric structure in a volatilememory device, wherein the volatile memory device is defined with a cellregion where a first NMOS transistor for use in a memory cell is formedand a peripheral region where a PMOS transistor for use in a logiccircuit and a second NMOS transistor for use in a logic circuit areformed, including the steps of: sequentially forming a first oxidelayer, a dielectric layer for trapping charges and a second oxide layeron a substrate; selectively etching the second oxide layer and thedielectric layer in a first predetermined region of the peripheralregion where the second NMOS transistor is formed; selectively etching aportion of the second oxide layer in a second predetermined region ofthe peripheral region where the PMOS transistor is formed to make thesecond oxide layer have a decreased thickness; removing the first oxidelayer exposed in the first. predetermined region as simultaneously asremoving the second oxide layer in the second predetermined region and aportion of the second oxide layer in the cell region; and forming athird oxide layer in the cell region and the peripheral region.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention willbecome better understood with respect to the following description ofthe preferred embodiments given in conjunction with the accompanyingdrawings, in which:

FIG. 1 is a cross-sectional view showing a transistor of a conventionaldynamic random access memory (DRAM) device;

FIG. 2A is a graph showing that a characteristic of junction leakageincreasing in proportion to a doping concentration of boron into aP-type well;

FIG. 2B is a graph showing that a data retention time decreases as adoping concentration of a P-type well increases;

FIG. 3 is a cross-sectional view showing a transistor of a DRAM devicewherein the transistor has a gate dielectric structure of oxide, nitrideand oxide (ONO) in accordance with the present invention;

FIG. 4A shows cross-sectional views of a DRAM device provided with NMOStransistors in a cell region having a gate dielectric structure of ONOand NMOS and PMOS transistors in a peripheral region having a gatedielectric structure of a single oxide layer in accordance with a firstembodiment of the present invention;

FIG. 4B shows cross-sectional views of a DRAM device provided with NMOStransistors in a cell region and a PMOS transistor in a peripheralregion each having a gate dielectric structure of ONO and an NMOStransistor in the peripheral region having a gate dielectric structureof a single oxide layer in accordance with a second and a thirdembodiments of the present invention;

FIGS. 5A to 5D are cross-sectional views illustrating a method forfabricating the DRAM device shown in FIG. 4A in accordance with thefirst embodiment of the present invention;

FIGS. 6A to 6D are cross-sectional views illustrating a method forfabricating the DRAM device shown in FIG. 4B in accordance with thesecond embodiment of the present invention; and

FIGS. 7A to 7E are cross-sectional views illustrating a method forfabricating the DRAM device shown in FIG. 4B in accordance with thethird embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A transistor of a volatile memory device with a gate dielectricstructure capable of trapping charges and a method for fabricating thesame in accordance with preferred embodiments of the present inventionwill be described in detail with reference to the accompanying drawings.

FIG. 3 is a cross-sectional view showing a transistor of a dynamicrandom access memory (DRAM) device in accordance with the presentinvention. Herein, the transistor has a gate dielectric structure ofoxide, nitride and oxide (ONO).

As shown, two wells 303 and 304 are formed in a silicon substrate 301.In a DRAM device, a transistor in a cell region is typically anN-channel transistor, while a P-channel transistor is used in aperipheral circuit region. Thus, the two wells are a deep N-type well303 formed in the silicon substrate 301 of P-type and a deep P-type well304 defined within the N-type well 303.

A device isolation layer 302 is formed in the silicon substrate 301 byperforming a shallow trench isolation (STI) method. After the formationof the device isolation layer 302, an active region and a field regionin which the device isolation layer 302 is formed are defined.

Next, a plurality of gate dielectric structures 350 are formed in theactive region of the silicon substrate 301. Then, a plurality of gates309 are formed on the corresponding gate dielectric structures 350. Achannel ion implantation region 305 for controlling a threshold voltageis formed in each of channel regions defined within portions of theP-type well 304 disposed beneath the corresponding gates 309. Also,there is a source/drain 311 in each predetermined region of the siliconsubstrate 301 allocated between the gates 309.

Herein, the gate dielectric structure 350 includes a first oxide layer306, which is a bottom gate dielectric layer, a nitride layer 307, whichis a middle gate dielectric layer and serves as a charge trapping layer,and a second oxide layer 308, which is a top gate dielectric layer. Inother words, the gate dielectric structure 350 has a structure of oxide,nitride and oxide (ONO).

Especially, the nitride layer 307 of the gate dielectric structure 350plays a role in increasing a threshold voltage of a transistor in a cellregion by capturing electrons during sequential processes forfabricating a semiconductor device. This increased threshold voltage canbe offset by the channel ion implantation region 305 having a lowconcentration. As a result, the transistor in accordance with thepresent invention can obtain an intended threshold voltage along withthe channel ion implantation region 305 having a low concentration,thereby obtaining a lowered potential. This lowered potential furtherresults in improvements on junction leakage and refresh characteristics.

Meanwhile, the DRAM device in accordance with the present invention hasa separate voltage generator for controlling a threshold voltage byimplanting charges, e.g., electrons or holes, to the gate dielectricstructure of the transistor. Because of this separate voltage generator,it is possible to control a threshold voltage after the fabrication ofthe transistor. If the threshold voltage needs to be controlleddepending on the use of a circuit, the threshold voltage can becontrolled by implanting electrons or holes to the nitride layer 307 ofthe gate dielectric structure 350 by supplying a predetermined voltageindividually to a gate, a drain and a source. This control of thethreshold voltage on operation of the transistor of the DRAM device withthe gate dielectric structure of ONO is shown in Table 1 provided below.Herein, the gate, the drain and the source are a word line, a bit lineBL and a storage node (SN) of a capacitor, respectively. TABLE 1 P-wellin Cell Region Gate BL SN (=Bulk) Remarks V_(TH) V_(p) 0 V 0 V OV orV_(BB) Control to control 11 increase V_(TH) through V_(TH) V_(p) V_(p)OV 0 V or V_(BB) electron control 12 implantation V_(TH) 0 V or V_(N)V_(p) V_(p) V_(p) Control to control 21 decrease V_(TH) V_(TH) OV orV_(N) V_(p) 0 OV or V_(BB) through hole control 22 implantation Read/0˜V_(PP) 0˜V_(DL) 0˜V_(DL) V_(BB) Same as a Write conventional operationrecipe

Herein, ‘V_(P)’, ‘V_(PP)’ and ‘V_(DL)’ are greater than approximatelyOV, and V_(N) and V_(BB) are less than approximately OV.

As shown in Table 1, when a voltage is supplied to the gate, the drainand the source as like the case of V_(TH) control 11 and the V_(TH)control 12, electrons are implanted into the nitride layer of the gatedielectric structure, thereby increasing the threshold voltage. On theother hand, when a voltage is supplied individually to the gate, thedrain, the source, and the P-well, holes are implanted into the nitridelayer of the gate dielectric structure, thereby decreasing the thresholdvoltage.

Eventually, in a conventional transistor of a DRAM device, it isrequired to optimize a punch-through voltage, a refresh time and athreshold voltage simultaneously. However, the transistor having thegate dielectric structure of ONO in accordance with the presentinvention is first fabricated by simultaneously optimizing thepunch-through voltage and the refresh time under consideration of anamount of captured charges during the formation of the nitride layer ofthe gate dielectric structure of ONO. The threshold voltagecharacteristic can be optimized after the fabrication of the abovetransistor depending on needs.

As shown in Table 1, as like the read and write operation in theconventional DRAM device, wherein the transistor has only an oxide layeras the gate dielectric structure, the read and write operation on dataof the DRAM device can be driven with a high speed under a low voltage.

FIGS. 4A and 4B are cross-sectional views showing a DRAM deviceintegrated with N-channel metal oxide semiconductor (NMOS) transistorsin a cell region and P-channel metal oxide semiconductor (PMOS) and NMOStransistors in a logic circuit region, i.e., a peripheral region.Particularly, FIG. 4A shows a first embodiment that the NMOS transistorsin the cell region have a gate dielectric structure of ONO and the NMOSand PMOS transistors in the peripheral region have a gate dielectricstructure of a single oxide layer. FIG. 4B shows that the NMOStransistors in the cell region and the PMOS transistor in the peripheralregion individually have a gate dielectric structure of ONO and the NMOStransistor in the peripheral region has a gate dielectric structure of asingle oxide layer in accordance with a second and a third embodimentsof the present invention. Also, it should be noted that the samereference numerals are used for the same constitution elements describedin the first embodiment and the second embodiment.

Referring to FIG. 4A, each of the NMOS transistors in the cell regionhas a gate dielectric structure 450 of ONO including a first oxide layer410, a nitride layer 411 and a second oxide layer 413A. Herein, thefirst oxide layer 410, the nitride layer 411 and the second oxide layer413A are a bottom gate dielectric layer, a middle gate dielectric layerfunctioning as a charge trapping layer and a top gate dielectric layer,respectively. On the other hand, the NMOS transistor and the PMOStransistor in the peripheral region individually have a gate dielectricstructure of a single oxide layer, denoted with a reference numeral 413Bfor the PMOS transistor and with a reference numeral 413C for the NMOStransistor.

Herein, an effective thickness (T_(OX)) of the gate dielectric structure450 including the first oxide layer 410, the oxide layer 411 and thesecond oxide layer 413A in the cell region is equal to or greater thanthat of the gate dielectric structure of the single oxide layer 413B or413C in the peripheral region.

Also, as described above, the nitride layer 411 of the gate dielectricstructure 450 in the cell region serves as the charge trapping layer. Inaddition to the use of nitride for the charge trapping layer, it isstill possible to use aluminum oxide and hafnium oxide capable ofcapturing charges.

More specific to the first embodiment, in the cell region where the NMOStransistors are formed, a deep N-type well 403 is formed in a substrate401, and a deep P-type well 404 is defined within the deep N-type well403. A plurality of gate dielectric structures 450 are formed onpredetermined portions of the P-type well 403. Herein, as describedabove, each of the gate dielectric structures 450 includes the firstoxide layer 410, the nitride layer 411 and the second oxide layer 413A.Also, a plurality of gates 414A are formed on the corresponding gatedielectric structures 450. Also, a gate insulation layer 415 is formedon each of the gate 414A. Also, there are channel ion implantationregions 407 each formed in a predetermined region disposed beneath thecorresponding gate 414A, i.e., each channel region of the P-type well404 and sources/drains 416A each formed in a predetermined region of thesubstrate 401 disposed between each two of the gates 414A.

Also, in the peripheral region where the PMOS transistors are formed,there is an N-type well 405 defined within a substrate 401. A gatedielectric structure of a single oxide layer 413B is formed on apredetermined portion of the N-type well 405. A gate 414B and a gateinsulation layer 415 are sequentially formed on the gate dielectricstructure of the single oxide layer 413B. A channel ion implantationregion 408 is formed in a channel region of the N-type well 405 disposedbeneath the gate 414B and the gate dielectric structure of the singleoxide layer 413B, and a source/drain 416B is formed in eachpredetermined region of the substrate 401 disposed beneath each lateralside of the gate 414B.

Further, in the peripheral region where the NMOS transistor is formed,there is a P-type well 406 defined within the substrate 401. A gatedielectric structure of a single oxide layer 413C is formed on apredetermined portion of the P-type well 406. A gate 414C and a gateinsulation layer 415 are sequentially formed on the gate dielectricstructure of the single oxide layer 413C. A channel ion implantationregion 409 is formed in a channel region of the P-type well 406 disposedbeneath the gate 414C and the gate dielectric structure of the singleoxide layer 413C, and a source/drain 416C is formed in eachpredetermined region of the substrate 401 disposed beneath each lateralside of the gate 414C.

Referring to FIG. 4B, in a cell region where NMOS transistors areformed, a deep N-type well 403 is formed in a substrate 401, and a deepP-type well 404 is defined within the deep N-type well 403. A pluralityof gate dielectric structures 450A are formed on predetermined portionsof the P-type well 404. Herein, each of the gate dielectric structures450A includes a first oxide layer 410A, a nitride layer 411A and asecond oxide layer 413A. The nitride layer 411A is a charge trappinglayer. Also, a plurality of gates 414A are formed on the correspondinggate dielectric structures 450A. A gate insulation layer 415 is thenformed on each of the gates 414A. Also, there are channel ionimplantation regions 407 each formed in a predetermined region disposedbeneath the gate 414A and the gate dielectric structure 450A, i.e., eachchannel region of the P-type well 404, and sources/drains 416A eachformed in a predetermined portion of the substrate 401 disposed betweeneach two of the gates 414A.

In a peripheral region where an NMOS transistor is formed, a deep N-typewell 405 is formed in a substrate 401. A gate dielectric structure 450Bis formed on a predetermined portion of the P-type well 405. Herein, thegate dielectric structure 450B includes a first oxide layer 410B, anitride layer 411B and a second oxide layer 413B. A gate 414B and a gateinsulation layer 415 are then sequentially formed on the gate dielectricstructure 450B. Also, there are a channel ion implantation region 408formed in a predetermined region disposed beneath the gate 414B and thegate dielectric structure 450B, i.e., a channel region of the N-typewell 405, and a source/drain 416B formed in each predetermined portionof the substrate 401 disposed beneath each lateral side of the gate414B.

Further, in the peripheral region where an NMOS transistor is formed,there is a P-type well 406 defined within the substrate 401. A gatedielectric structure of a single oxide layer 413C is formed on apredetermined portion of the P-type well 406. A gate 414C and a gateinsulation layer 415 are sequentially formed on the gate dielectricstructure of the single oxide layer 413C. A channel ion implantationregion 409 is formed in a channel region of the P-type well 406 disposedbeneath the gate 414C and the gate dielectric structure of the singleoxide layer 413C, and a source/drain 416C is formed in eachpredetermined region of the substrate 401 disposed beneath each lateralside of the gate 414C.

In accordance with the second and the third embodiments, a thickness ofan effective oxide layer of the gate dielectric structure 450A in thecell region is equal to or greater than that of an effective oxide layerof the gate dielectric structure 450B in the peripheral region and thatof an effective oxide layer of the gate dielectric structure of thesingle oxide layer 413C in the peripheral region. Also, the nitridelayer 411A of the gate dielectric structure 450A in the cell region is acharge trapping layer, and can be replaced with an oxynitride layer,aluminum oxide layer, or a hafnium oxide layer capable of trappingcharges.

FIGS. 5A to 5D are cross-sectional views illustrating a method forfabricating the DRAM device shown in FIG. 4A.

Referring to FIG. 5A, a field oxide layer 502 is formed in a substrate501 made of silicon. In a cell region, a deep N-type well 503 and a deepP-type well 504 are formed. In a peripheral region, an N-type well 505and a P-type well 506 are formed. A P-type impurity is ion implantedinto each of the P-type wells 504 and 506 formed in the cell region andthe peripheral region, respectively, thereby forming channel ionimplantation regions 507 and 509 in the cell region and the peripheralregion, respectively. Meanwhile, an N-type impurity is ion implantedinto the N-type well 505 to form a channel ion implantation region 508in the peripheral region.

Next, a gate dielectric structure is formed. More specifically, a firstoxide layer 510, which is a bottom gate dielectric layer, is formed onthe substrate 501. Then, a middle gate dielectric layer 511 is formed onthe first oxide layer 510. Herein, the middle gate dielectric layer 511is made of a material capable of trapping charges, and this type ofmaterial is selected from a group consisting of nitride, oxynitride,alumina (Al₂O₃) and hafnium oxide (HfO₂). The oxynitride layer can beformed by applying a dinitrogen oxide (N₂O) treatment or a nitrogenoxide (NO) treatment to the first oxide layer 510. After the formationof the middle gate dielectric layer 511, a second oxide layer 512 isformed on the middle gate dielectric layer 511. Herein, the second oxidelayer 512 serves as a buffer oxide layer.

Referring to FIG. 5B, although not illustrated, a photosensitive layeris formed on the above resulting substrate structure and is patternedsuch that the photosensitive layer remains in the cell region. Thesecond oxide layer 512 and the middle gate dielectric layer 511 in theperipheral region are etched. Then, the photosensitive layer is removed,and the first oxide layer 510 in the peripheral region is etchedthereafter. When the first oxide layer 510 in the peripheral region isetched, the second oxide layer 512 in the cell region is etched away, ora portion of the second oxide layer 512 remains. Herein, the etchingprocess proceeds by performing one of a dry etching process or a wetetching process.

Referring to FIG. 5C, a third oxide layer 513 serving as a top gatedielectric layer is formed on the middle gate dielectric layer 511 inthe cell region, while in the peripheral region, the third oxide layer513 is formed on the substrate 501. Herein, in the cell region, a gatedielectric structure including the first oxide layer 510, the middlegate dielectric layer 511 and the third oxide layer 513 is formed.

At this time, the third oxide layer 513 is preferably formed byperforming a thermal oxidation process. In case that the middle gatedielectric layer 511 is made of nitride, a thickness of the third oxidelayer 513 formed on the nitride-based middle gate dielectric layer 511in the cell region is thinner than that of the third oxide layer 513formed in the peripheral region. Thus, it is preferable to control athickness of the remaining second oxide layer 512, or to control thethickness of the third oxide layer 513 such that a thickness of aneffective oxide layer of the gate dielectric structure in the cellregion is equal to or greater than a thickness of the third oxide layer513 in the peripheral region.

That is, when the second oxide layer 512 in the cell region is etched, aremaining thickness of the second oxide layer 512 is controlled to formthe gate dielectric structure in the cell region by including the firstoxide layer 510, the middle dielectric layer 511, the second oxide layer512 and the third oxide layer 513, or by including the first oxide layer510, the middle dielectric layer 511 and the third oxide layer 513 andto form the gate dielectric structure in the peripheral region byincluding only the third oxide layer 513.

Referring to FIG. 5D, a gate material 514 and a gate insulation layer515 are formed on the third oxide layer 513 and are then patterned byperforming an etching process with use of a gate mask. Afterwards,typical DRAM fabrication processes, e.g., a source/drain formationprocess, proceed to complete the fabrication of the DRAM device.

Meanwhile, the DRAM device shown in FIG. 4B is fabricated by the sameprocesses described in FIGS. 5A to 5D in the exception that a secondoxide layer and a middle gate dielectric layer disposed in a PMOS regionwhere a PMOS transistor is formed in the peripheral region are maskedduring the etching of the second oxide layer and the middle gatedielectric layer in the peripheral region.

With reference to FIGS. 6A to 6D and FIGS. 7A to 7E, detaileddescription on a method for fabricating the DRAM device shown in FIG. 4Bwill be described in detail hereinafter. Also, in FIGS. 6A to 7E, thesame reference numerals are used for the same constitution elementsdescribed in FIGS. 5A to 5D.

FIGS. 6A to 6D are cross-sectional views showing a method forfabricating the DRAM in accordance with a second embodiment of thepresent invention.

Referring to FIG. 6A, a field oxide layer 502 is formed in a substrate501 made of silicon. In a cell region, a deep N-type well 503 and a deepP-type well 504 are formed. In a peripheral region, an N-type well 505and a P-type well 506 are formed. A P-type impurity is ion implantedinto each of the P-type wells 504 and 506 respectively formed in thecell region and the peripheral region to form channel ion implantationregions 507 and 509 in the cell region and the peripheral region,respectively. Meanwhile, an N-type impurity is ion implanted into theN-type well 505 to form a channel ion implantation region 508 in theperipheral region.

Next, a gate dielectric structure is formed. More specifically, a firstoxide layer 510, which is a bottom gate dielectric layer, is formed onthe substrate 501. Then, a middle gate dielectric layer 511 is formed onthe first oxide layer 510. Herein, the middle gate dielectric layer 511is made of a material capable of trapping charges, and this type ofmaterial is selected from a group consisting of nitride, oxynitride,alumina (Al₂O₃) and hafnium oxide (HfO₂). The oxynitride layer can beformed by applying a dinitrogen oxide (N₂O) treatment or a nitrogenoxide (NO) treatment to the first oxide layer 510. After the formationof the middle gate dielectric layer 511, a second oxide layer 512 isformed on the middle gate dielectric layer 511. Herein, the second oxidelayer 512 serves as a buffer oxide layer.

Referring to FIG. 6B, in a predetermined region of the peripheral regionwhere an NMOS transistor will be formed (hereinafter referred to theNMOS region), the second oxide layer 512 and the middle gate dielectriclayer 511 are selectively are etched, thereby obtaining a patternedsecond oxide layer 512A and a patterned middle gate dielectric layer511A. Also, the etching process proceeds by employing one of a dryetching process or a wet etching process.

Referring to FIG. 6C, the first oxide layer 510 exposed in the NMOSregion is etched as simultaneously as the second oxide layer 512disposed in the cell region and the patterned second oxide layer 512A ina predetermined region of the peripheral region where a PMOS transistorwill be formed (hereinafter referred to as the PMOS region) are etched.After this etching process, a patterned middle gate dielectric layer511A and a patterned first oxide layer 510A are obtained in the PMOSregion.

Referring to FIG. 6D, a third oxide layer 513 serving as a top gatedielectric layer is formed on the above resulting structure. The thirdoxide layer 513 is preferably formed by performing a thermal oxidationprocess. Afterwards, a gate material 514 and a gate insulation layer 515are formed on the third oxide layer 513 and are then patterned byperforming an etching process with use of a gate mask. Afterwards,typical DRAM fabrication processes, e.g., a source/drain formationprocess, proceed to complete the fabrication of the DRAM device.

FIGS. 7A to 7E are cross-sectional views showing a method forfabricating the DRAM device in accordance with a third embodiment of thepresent invention.

Referring to FIG. 7A, a first oxide layer 510, a middle gate dielectriclayer 511 and a second oxide layer 512 are sequentially formed on asemi-finished substrate structure including various device elements.Herein, the semi-finished substrate structure is prepared by using thesame processes described in FIGS. 5A to 5D, and detailed description onthe employed processes is omitted. Herein, the middle gate dielectriclayer 511 is made of a material capable of trapping charges, and thistype of material is selected from a group consisting of nitride,oxynitride, Al₂O₃ and HfO₂. The oxynitride layer can be formed byapplying an N₂O treatment or an NO treatment to the first oxide layer510. Also, the second oxide layer 512 serves' as a buffer oxide layer.

Referring to FIG. 7B, in an NMOS region, the second oxide layer 512 andthe middle dielectric layer 511 are selectively etched, therebyobtaining a patterned second oxide layer 512A and a patterned middlegate dielectric layer 511A. At this time, the etching process proceedsby employing one of a dry etching process and a wet etching process.

As shown in FIG. 7C, a portion of the patterned second oxide layer 512Ain a PMOS region is selectively etched.

Referring to FIG. 7D, the first oxide layer 510 exposed in the NMOSregion and a remaining portion of the patterned second oxide layer 512Ain the PMOS region are removed. As simultaneously as these removals, aportion of the second oxide layer 512 in the cell region is alsoremoved. Herein, a remaining portion of the second oxide layer 512 isdenoted with a reference numeral 512A.

Referring to FIG. 7E, a third oxide layer 513 serving as a top gatedielectric layer is formed on the above resulting structure. The thirdoxide layer 513 is preferably formed by performing a thermal oxidationprocess. Afterwards, a gate material 514 and a gate insulation layer 515are formed on the third oxide layer 513 and are then patterned byperforming an etching process with use of a gate mask. Afterwards,typical DRAM fabrication processes, e.g., a source/drain formationprocess, proceed to complete the fabrication of the DRAM device.

As described in the above first to third embodiments of the presentinvention, through a complete removal of the second oxide layer in thecell region and in the peripheral region, or through a control of aremaining thickness of the second oxide layer, it is possible to make athickness of an effective oxide layer of a gate dielectric structure inthe cell region and that of an effective oxide layer of a gatedielectric structure in the PMOS region equal to or greater than that ofa gate dielectric structure in the NMOS region, or to make a thicknessof the effective oxide layer of the gate dielectric structure in thePMOS region equal to that of the effective oxide layer of the gatedielectric structure in the NMOS region, but less than that of theeffective oxide layer of the gate dielectric structure in the cellregion.

That is, by controlling an etch target thickness of the second oxidelayer when the second oxide layer formed in the cell region and the PMOSregion is etched, the gate dielectric structure in the cell region andthat in the PMOS region of the peripheral region includes the firstoxide layer, the middle dielectric layer capable of trapping charges,the remaining portion of the second oxide layer and the third oxidelayer 513, or includes the first oxide layer, the middle dielectriclayer and the third oxide layer, while the gate dielectric structure inthe NMOS region of the peripheral region includes only the third oxidelayer.

It is also possible to make the gate dielectric structure in the cellregion include the first oxide layer, the middle dielectric layer, theremaining second oxide layer and the third oxide layer, while the gatedielectric structure in the PMOS transistor includes the first oxidelayer, the middle dielectric layer and the third oxide layer. At thistime, the gate dielectric structure in the NMOS region of the peripheralregion includes only the third oxide layer.

In accordance with the first to the third embodiments of the presentinvention, it is possible to control a threshold voltage value by usinga nitride layer capable of trapping charges as a dielectric layer. Thus,even if the design rule is decreased to below approximately 100 nm, adoping concentration of the channel ion implantation region can bedecreased, thereby improving a junction leakage current characteristicand a refresh characteristic as simultaneously as obtaining an intendedthreshold voltage value and a punch-through characteristic.

The present application contains subject matter related to the Koreanpatent application No. KR 2004-0019363, filed in the Korean PatentOffice on Mar. 22, 2004, the entire contents of which being incorporatedherein by reference.

While the present invention has been described with respect to certainpreferred embodiments, it will be apparent to those skilled in the artthat various changes and modifications may be made without departingfrom the spirit and scope of the invention as defined in the followingclaims.

1. A transistor in a cell region of a volatile memory device, thetransistor comprising: a substrate of a first conductive type; a gatedielectric structure capable of trapping charges and formed on thesubstrate; a gate formed on the gate dielectric structure; a gateinsulation layer formed on the gate; a source/drain of a secondconductive type formed in a predetermined region of the substratedisposed beneath each lateral side of the gate; and a channel ionimplantation region of the first conductive type formed in apredetermined region of the substrate disposed beneath the gate.
 2. Thetransistor of claim 1, wherein the gate dielectric structure includes: abottom gate dielectric layer formed on the substrate; a middle gatedielectric layer for trapping charges formed on the bottom gatedielectric layer; and a top gate dielectric layer formed on the middledielectric layer.
 3. The transistor of claim 2, wherein the middle gatedielectric layer is implanted with electrons to increase a thresholdvoltage value.
 4. The transistor of claim 2, wherein the middledielectric layer is implanted with holes to decrease a threshold voltagevalue.
 5. The transistor of claim 2, wherein the bottom gate dielectriclayer and the top gate electric layer are made of oxide and the middledielectric layer is made of nitride.
 6. The transistor of claim 2,wherein the bottom gate dielectric layer and the top gate dielectriclayer are made of oxide and the middle gate dielectric layer is made ofa material selected from a group consisting of oxynitride, aluminumoxide and hafnium oxide.
 7. A volatile memory device, comprising: afirst transistor for use in a memory cell provided with a gatedielectric structure including: a bottom gate dielectric layer; a middlegate dielectric layer for trapping charges; and a top gate dielectriclayer; and a second transistor for use in a logic circuit provided witha gate dielectric structure of a single oxide layer.
 8. The volatilememory device of claim 7, wherein an effective oxide layer of the gatedielectric structure of the first transistor has a thickness equal tothat of an effective oxide layer of the gate dielectric structure of thesecond transistor.
 9. The volatile memory device of claim 7, wherein aneffective oxide layer of the gate dielectric structure of the firsttransistor has a thickness greater than that of an effective oxide layerof the gate dielectric structure of the second transistor.
 10. Thevolatile memory device of claim 7, wherein the middle dielectric layerof the first transistor is implanted with electrons to increase athreshold voltage value.
 11. The volatile memory device of claim 7,wherein the middle dielectric layer of the first transistor is implantedwith holes to decrease a threshold voltage value.
 12. The volatilememory device of claim 7, wherein in the gate dielectric structure ofthe first transistor, the bottom gate dielectric layer and the top gatedielectric layer are made of oxide and the middle dielectric layer ismade of nitride.
 13. The volatile memory device of claim 7, wherein inthe gate dielectric structure of the first transistor, the bottom gatedielectric layer and the top gate dielectric layer are made of oxide andthe middle dielectric layer is made of a material selected from a groupconsisting of oxynitride, aluminum oxide and hafnium oxide.
 14. Avolatile memory device, comprising: a first N-channel metal oxidesemiconductor (NMOS) transistor for use in a memory cell provided with agate dielectric structure including: a bottom gate dielectric layer; amiddle gate dielectric layer; and a top gate dielectric layer; a secondNMOS transistor for use in a logic circuit provided with a gatedielectric structure of a single oxide layer; and a P-channel metaloxide semiconductor (PMOS) transistor for use in a logic circuitprovided with a gate dielectric structure including: a bottom gatedielectric layer; a middle gate dielectric layer; and a top gatedielectric layer.
 15. The volatile memory device of claim 14, wherein aneffective oxide layer of the gate dielectric structure of the first NMOStransistor and an effective oxide layer of the gate dielectric structureof the PMOS transistor have a thickness equal to that of the gatedielectric structure of the second NMOS transistor.
 16. The volatilememory device of claim 14, wherein an effective oxide layer of the gatedielectric structure of the first NMOS transistor and an effective oxidelayer of the gate dielectric structure of the PMOS transistor have athickness greater than that of an effective oxide layer of the gatedielectric structure of the second NMOS transistor.
 17. The volatilememory device of claim 14, wherein an effective oxide layer of the gatedielectric structure of the PMOS transistor has a thickness equal tothat of an effective oxide layer of the gate dielectric structure of thesecond NMOS transistor, and an effective oxide layer of the gatedielectric structure of the first NMOS transistor has a thicknessgreater than that of the effective oxide layer of the gate dielectricstructure of the PMOS transistor and that of the effective oxide layerof the gate dielectric structure of the second NMOS transistor.
 18. Thevolatile memory device of claim 14, wherein each middle dielectric layerof the first NMOS transistor and the PMOS transistor is implanted withelectrons to increase a threshold voltage.
 19. The volatile memorydevice of claim 14, wherein each middle dielectric layer of the firstNMOS transistor and the PMOS transistor are implanted with holes todecrease a threshold voltage.
 20. The volatile memory device of claim14, wherein each bottom gate dielectric layer and each top gatedielectric layer of the first NMOS transistor and the PMOS transistorare made of oxide and each middle gate dielectric layer of the firstNMOS transistor and the PMOS transistor is made of nitride.
 21. Thevolatile memory device of claim 14, wherein each bottom gate dielectriclayer and each top gate dielectric layer of the first NMOS transistorand the PMOS transistor are made of oxide and each middle gatedielectric layer of the first NMOS transistor and the PMOS transistor ismade of a material selected from a group consisting of oxynitride,aluminum oxide and hafnium oxide.
 22. A volatile memory device,comprising: a transistor for use in a memory cell, the transistorincluding: a substrate of a first conductive; a gate dielectricstructure capable of trapping charges and formed on the substrate; agate formed on the gate dielectric structure; a gate insulation layerformed on the gate; a source/drain of a second conductive type formed ina predetermined portion of the substrate disposed beneath each lateralside of the gate; and a channel ion implantation region of the firstconductive type formed in a predetermined region of the substratedisposed beneath the gate; and a voltage generating means forcontrolling a threshold voltage of the transistor for use in the memorycell by implanting charges to the gate dielectric structure throughsupplying a predetermined voltage to each of the substrate, the gate andthe source/drain.
 23. The volatile memory device of claim 22, whereinthe gate dielectric structure includes: a bottom gate dielectric layerformed on the substrate; a middle gate dielectric layer for trappingcharges formed on the bottom gate dielectric layer; and a top gatedielectric layer formed on the middle gate dielectric layer.
 24. Thevolatile memory device of claim 23, wherein the voltage generating meansincreases a threshold voltage of the transistor for use in the memorycell by implanting electrons to the middle gate dielectric layer. 25.The volatile memory device of claim 23, wherein the voltage generatingmeans decreases a threshold voltage of the transistor for use in thememory cell by implanting holes to the middle gate dielectric layer. 26.The volatile memory device of claim 23, wherein the bottom gatedielectric layer and the top gate dielectric layer are made of oxide andthe middle gate dielectric layer is made of nitride.
 27. The volatilememory device of claim 23, wherein the bottom gate dielectric layer andthe top gate dielectric layer are made of oxide and the middle gatedielectric layer is made of a material selected from a group consistingof oxynitride, aluminum oxide and hafnium oxide.
 28. In a method forforming a gate dielectric structure of a volatile memory device, whereinthe volatile memory device is defined with a cell region where atransistor for use in a memory cell is formed and a peripheral regionwhere a transistor for use in a logic circuit is formed, the methodcomprising the steps of: sequentially forming a first oxide layer, adielectric layer for trapping charges and a second oxide layer on asubstrate; selectively etching the second oxide layer and the dielectriclayer disposed in the peripheral region; etching the first oxide layerexposed in the peripheral region as simultaneously as etching the secondoxide layer in the cell region; and forming a third oxide layer in thecell region and in the peripheral region.
 29. The method of claim 28,wherein at the step of etching the second oxide layer in the cellregion, the second oxide layer is controlled to remain with apredetermined thickness so that the gate dielectric structure of thetransistor in the cell region includes the first oxide layer, thedielectric layer for trapping charges, the second oxide layer, and thethird oxide layer and the gate dielectric structure of the transistor inthe peripheral region includes the third oxide layer.
 30. The method ofclaim 28, wherein at the step of etching the second oxide layer in thecell region, the second oxide layer is controlled to remain with apredetermined thickness so that the gate dielectric structure of thetransistor in the cell region include the first oxide layer, thedielectric layer for trapping charges and the third oxide layer and thegate dielectric structure of the transistor in the peripheral regionincludes the third oxide layer.
 31. The method of claim 28, wherein thedielectric layer for trapping charges is made of a material selectedfrom a group consisting of nitride, oxynitride, aluminum oxide andhafnium oxide.
 32. In a method for forming a gate dielectric structurein a volatile memory device, wherein the volatile memory device isdefined with a cell region where a first NMOS transistor for use in amemory cell is formed and a peripheral region where a second NMOStransistor for use in a logic circuit and a PMOS transistor for use in alogic circuit are formed, the method comprising the steps of:sequentially forming a first oxide layer, a dielectric layer fortrapping charges and a second oxide layer on a substrate; selectivelyetching the second oxide layer and the dielectric layer in a firstpredetermined region of the peripheral region where the second NMOStransistor is formed; removing the first oxide layer exposed in thefirst predetermined region as simultaneously as etching the second oxidelayer disposed in the cell region and in a second predetermined regionof the peripheral region where the PMOS transistor is formed; andforming a third oxide layer in the cell region and in the peripheralregion.
 33. The method of claim 32, wherein at the step of etching thesecond oxide layer in the cell region and the first predetermined regionof the peripheral region, the second oxide layer is controlled to beetched with a predetermined thickness so that each gate dielectricstructure of the first NMOS transistor and the PMOS transistor includesthe first oxide layer, the dielectric layer for trapping charges, aremaining portion of the second oxide layer and the third oxide layerand the gate dielectric structure of the second NMOS transistor includesthe third oxide layer.
 34. The method of claim 32, wherein at the stepof etching the second oxide layer in the cell region and the firstpredetermined region of the peripheral region, the second oxide layer iscontrolled to remain with a predetermined thickness so that each gatedielectric structure of the first NMOS transistor and the PMOStransistor includes the first oxide layer, the dielectric layer fortrapping charges and the third oxide layer and the gate dielectricstructure of the second NMOS transistor includes the third oxide layer.35. The method of claim 32, wherein the dielectric layer for trappingcharges is made of a material selected from a group consisting ofnitride, oxynitride, aluminum oxide and hafnium oxide.
 36. In a methodfor forming a gate dielectric structure in a volatile memory device,wherein the volatile memory device is defined with a cell region where afirst NMOS transistor for use in a memory cell is formed and aperipheral region where a PMOS transistor for use in a logic circuit anda second NMOS transistor for use in a logic circuit are formed, themethod comprising the steps of: sequentially forming a first oxidelayer, a dielectric layer for trapping charges and a second oxide layeron a substrate; selectively etching the second oxide layer and thedielectric layer in a first predetermined region of the peripheralregion where the second NMOS transistor is formed; selectively etching aportion of the second oxide layer in a second predetermined region ofthe peripheral region where the PMOS transistor is formed to make thesecond oxide layer have a decreased thickness; removing the first oxidelayer exposed in the first predetermined region as simultaneously asremoving the second oxide layer in the second predetermined region and aportion of the second oxide layer in the cell region; and forming athird oxide layer in the cell region and the peripheral region.
 37. Themethod of claim 36, wherein at the step of etching the second oxidelayer in the second predetermined region and in the cell region, thesecond oxide layer is controlled to be etched with a predeterminedthickness, so that the gate dielectric structure of the first NMOStransistor includes the first oxide layer, the dielectric layer fortrapping charges, a remaining portion of the second oxide layer and thethird oxide layer; the gate dielectric structure of the PMOS transistorincludes the first oxide layer, the dielectric layer for trappingcharges and the third oxide layer; and the gate dielectric structure ofthe second NMOS transistor includes the third oxide layer.
 38. Themethod of claim 36, wherein the dielectric layer for trapping charges ismade of a material selected from a group consisting of nitride,oxynitride, aluminum oxide and hafnium oxide.